Funded by: Siemens
Researchers: Hayk Nersisyan, Aram Butavyan
Project description
As semiconductor chips become increasingly compact and complex, thermal management has emerged as a major challenge in electronic design. Heat dissipation depends strongly on the internal arrangement of metal and dielectric materials, and current practice relies on detailed finite-element simulations to estimate effective thermal conductivity. Although these simulations are accurate, they are computationally expensive and difficult to apply at the scale required for modern chip design. This project addresses that limitation by developing a machine learning model that can predict thermal conductivity directly from the microstructure layout, enabling much faster thermal assessment during the design process.
In this work, each chip section is represented as a binary image in which metal and dielectric regions are encoded by different values. Using these images, we trained a residual convolutional neural network to predict the effective thermal conductivity components of the structure. The model was designed to capture the geometric and physical characteristics that govern heat transport in metal-dielectric composites. Residual feature extraction, multi-scale dilated convolutions, direction-aware strip convolutions, attention mechanisms, and global metal-density information were combined to identify thermally important pathways and improve predictive accuracy.
A second component of the project explored compact feature representations for thermal prediction. Starting from high-resolution microstructure images of size 1000 x 1000 pixels, the study investigated how much information is truly needed to characterize a structure’s thermal behavior. The network was trained to compress each image into a small learned representation, or thermal “fingerprint,” and multiple strategies for generating this compact representation were compared. The results showed that learned, task-driven summaries provide the best balance between compression and predictive performance.
The resulting model achieved very strong predictive performance on the test set, with an overall R² of approximately 0.99 and low prediction error across all three conductivity components. These results indicate that the model can serve as a practical surrogate for costly physical simulations, substantially accelerating the evaluation of chip layouts. Beyond fast prediction, the framework also provides a basis for identifying unusual or potentially problematic structures at an early stage, making it a promising tool for thermal-aware chip design in industrial workflows.
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